XC164-16 Datasheet, PDF (44/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.2
Timer Block GPT2
From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as
summarized below. Those portions of port and direction registers which are used for
alternate functions by the GPT2 block are shaded.
Data Registers
T5
T6
CAPREL
Control Registers
T5CON
T6CON
SYSCON3
Interrupt Control
T5IC
T6IC
CRIC
Port Registers
ODP3
E
DP3
P3
ALTSEL0P3 E
P5
P5DIDIS
Tx
CAPREL
TxCON
TxIC
SYSCON3
GPT2 Timer x Register
GPT2 Capture/Reload Register
GPT2 Timer x Control Register
GPT2 Timer x Interrupt Ctrl. Reg.
System Ctrl. Reg. 3 (Per. Mgmt.)
ODP3
DP3
P3
ALTSEL0P3
P5
P5DIDIS
Port 3 Open Drain Control Register
Port 3 Direction Control Register
Port 3 Data Register
Port 3 Alternate Output Select Reg.
Port 5 Data Register
Port 5 Digital Input Disable Reg.
mc_gpt0107_registers.vsd
Figure 14-19 SFRs Associated with Timer Block GPT2
Both timers of block GPT2 (T5, T6) can run in one of 3 basic modes: Timer Mode, Gated
Timer Mode, or Counter Mode. All timers can count up or down. Each timer of GPT2 is
controlled by a separate control register TxCON.
Each timer has an input pin TxIN (alternate pin function) associated with it, which serves
as the gate control in gated timer mode, or as the count input in counter mode. The count
direction (up/down) may be programmed via software or may be dynamically altered by
a signal at the External Up/Down control input TxEUD (alternate pin function). An
overflow/underflow of core timer T6 is indicated by the Output Toggle Latch T6OTL,
whose state may be output on the associated pin T6OUT (alternate pin function). The
auxiliary timer T5 may additionally be concatenated with core timer T6 (through T6OTL).
The Capture/Reload register CAPREL can be used to capture the contents of timer T5,
or to reload timer T6. A special mode facilitates the use of register CAPREL for both
functions at the same time. This mode allows frequency multiplication. The capture
function is triggered by the input pin CAPIN, or by GPT1 timer’s T3 input lines T3IN and
T3EUD. The reload function is triggered by an overflow or underflow of timer T6.
Overflows/underflows of timer T6 may also clock the timers of the CAPCOM units.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer count registers T5 or T6, located in the non-bitaddressable SFR
User’s Manual
GPT_X41, V2.0
14-31
V2.1, 2004-03