XC164-16 Datasheet, PDF (209/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
18.7
Output Modulation Control
The last block of the data path is the Output Modulation Control Logic. Here, all the
modulation sources are combined and control the actual level of the output pins.
In the following, the six T12-related outputs (CC6x, COUT6x) are discussed separately
from the T13-related output CC63.
Figure 18-39 gives an overview on the six control blocks and control signals regarding
the T12-related outputs. Four individual modulation signals and their associated enable
controls lead to each one of the blocks. The modulation signals CC6x_O and
COUT6x_O come from the State Selection logic (see Figure 18-15) at the outputs of the
three State Bits CC6xST. Signals MCMPy are the six outputs of the Multi-Channel Mode
register MCMOUT (see Figure 18-31). Signal CC63_O is the T13-generated signal from
the State Selection logic at the output of the State Bit CC63_ST (see Figure 18-30), and
leads in parallel to all 6 blocks. The trap signal TRPS also is connected to all six blocks,
and is the output of the Trap State bit (see Figure 18-37).
While signals CC6x_O/COUT6x_O, CC63_O, and TRPS have individual enable controls
for each of the six blocks, there is only one general enable signal, MCMEN, for the
MCMPy signals.
The output of each of the modulation control blocks is connected to a level select block,
which offers the option to determine the actual output level of a pin, depending on the
state of the output line.
Figure 18-40 provides a closer look at one of the modulation and level select blocks. The
logic, which combines the various signals, is designed such that only signals which are
enabled by their respective enable signal can influence the output line, MCL_OUT. If one
of the modulation signals CC6x_O/COUT6x_O, CC63_O, or MCMPx is enabled and is
at passive state, output MCL_OUT is also in passive state, regardless of the state of the
other enabled signals. Only if all enabled signals are in active state output MCL_OUT
shows an active state.
If the Trap State is active (TRPS = 1), then all outputs for which the trap signal is enabled
(TRPENy = 1) are set to the passive state.
The output MCL_OUT of the modulation control block is then used to select the actual
level of the output, specified through the Passive State Select bit PSLy. When
MCL_OUT is in the passive state, the level specified directly by PSLy is output. When
MCL_OUT is in the active state, the inverted level of PSLy is output.
The PSLy bits have shadow registers to allow for updates without undesired pulses on
the output lines. The bits are updated with the T12 shadow transfer signal (T12_ST). A
read action returns the actually used values, whereas a write action targets the shadow
bits. Providing a shadow register for the PSL value as well as for other values related to
the generation of the PWM signal facilitates a concurrent update by software for all
relevant parameters (see also Section 18.8).
User’s Manual
CAPCOM6_X, V2.0
18-65
V2.1, 2004-03