XC164-16 Datasheet, PDF (333/417 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC164-16 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.6.2 Normal Gateway with FIFO Buffering
MMC_<d> = ‘01x’:
When the gateway destination object is programmed as FIFO buffer, bitfield CANPTR_<s>
is used as pointer to the FIFO element to be addressed as destination for the next copy
process. CANPTR_<s> has to be initialized with the message object number of the FIFO
base element on the destination side. CANPTR_<s> is automatically updated according to
the FIFO rules, when a data frame was copied to the indicated FIFO element on the
destination side. Bit GDFS_<s> determines if the TXRQ_<d> bit in the selected FIFO element
is set after reception of a data frame copied from the source side.
The base message object is indicated by <ba>, the slave message objects by <sl>. The
number of base and slave message objects, combined to a buffer on the destination
side, has to be a power of two (2, 4, 8 etc.) and the buffer base address has to be an
integer multiple of the buffer length. Bitfield CANPTR_<ba> of the FIFO base element and
bitfield CANPTR_<s> have to be initialized with the same start value (message object
number of the FIFO base element). CANPTR_<sl> of all FIFO slave elements must be
initialized with the message object number of the FIFO base element. Bitfield FSIZE_<d>
of all FIFO elements must contain the FIFO buffer length and has to be identical with the
content of FSIZE_<s>.
Figure 21-19 illustrates the operation of a normal gateway with a FIFO buffer on the
destination side.
User’s Manual
TwinCAN_X41, V2.1
21-33
V2.1, 2004-03