EP1SGX10DF672C6 Datasheet, PDF (94/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

TriMatrix Memory
M4K RAM blocks support byte writes when the write port has a data
width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be
masked so the device can write to specific bytes. The unwritten bytes
retain the previous written value. Table 4–6 summarizes the byte
selection.
Table 4–6. Byte Enable for M4K Blocks Notes (1), (2)
byteena[3..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
datain ×18
[8..0]
[17..9]
–
–
datain ×36
[8..0]
[17..9]
[26..18]
[35..27]
Notes to Table 4–6:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, that is, in ×16 and
×32 modes.
The M4K RAM blocks allow for different clocks on their inputs and
outputs. Either of the two clocks feeding the block can clock M4K RAM
block registers (renwe, address, byte enable, datain, and output
registers). Only the output register can be bypassed. The eight labclk
signals or local interconnects can drive the control signals for the A and B
ports of the M4K RAM block. LEs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in Figure 4–16.
The R4, R8, C4, C8, and direct link interconnects from adjacent LABs
drive the M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
resources. Up to 10 direct link input connections to the M4K RAM Block
are possible from the left adjacent LABs and another 10 possible from the
right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through 10 direct link interconnects each. Figure 4–17 shows
the M4K RAM block to logic array interface.
4–28
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005