EP1SGX10DF672C6 Datasheet, PDF (147/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Figure 4–50. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs Note (1)
PLL5_OUT[3..0] CLK14 (1)
PLL5_FB CLK15(2)
CLK12 (1) _CLK13 (2)
Regional
Clocks
RCLK2
RCLK3
Global
Clocks
Regional
Clocks
RCLK6
RCLK7
E[0..3]
PLL 5
PLL 11 (4)
L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1
L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1
PLL 6
PLL 12 (4)
PLL11_OUT
RCLK10
RCLK11
G12
G13
G14
G15
G4
G5
G6
G7
RCLK12
RCLK13
PLL12_OUT
PLL6_OUT[3..0] PLL6_FB
CLK6 (1)
CLK4 (1) CLK5(2)
Note to Figure 4–50:
(1) PLLs 5, 6, 11, and 12 are enhanced PLLs.
CLK7 (2)
Altera Corporation
February 2005
4–81
Stratix GX Device Handbook, Volume 1