EP1SGX10DF672C6 Datasheet, PDF (249/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–74. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2)
Standard
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
-5 Speed Grade
Min
Max
–110
–230
–230
–230
–30
–30
50
90
–50
100
20
230
0
380
190
380
390
-6 Speed Grade
Min
Max
–115
–241
–241
–241
–31
–31
53
95
–52
105
21
242
0
399
200
399
410
-7 Speed Grade
Unit
Min
Max
–133
ps
–277
ps
–277
ps
–277
ps
–36
ps
–36
ps
61
ps
109
ps
–60
ps
120
ps
24
ps
278
ps
0
ps
459
ps
230
ps
459
ps
471
ps
Table 6–75. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2)
Standard
LVCMOS
3.3-V LVTTL
2 mA
4 mA
8 mA
12 mA
24 mA
4 mA
8 mA
12 mA
16 mA
24 mA
-5 Speed Grade
Min
Max
570
570
350
130
0
570
350
130
70
0
-6 Speed Grade
Min
Max
599
599
368
137
0
599
368
137
74
0
-7 Speed Grade
Unit
Min
Max
689
ps
689
ps
423
ps
157
ps
0
ps
689
ps
423
ps
157
ps
85
ps
0
ps
Altera Corporation
June 2006
6–47
Stratix GX Device Handbook, Volume 1