EP1SGX10DF672C6 Datasheet, PDF (262/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

High-Speed I/O Specification
Table 6–87. High-Speed I/O Specifications (Part 2 of 4) Notes (1), (2)
Symbol
Conditions
f_HSDR Device
operation
(LVDS,
LVPECL,
HyperTransport
technology)
J = 10
J=8
J=7
J=4
J=2
J = 1 (LVDS and
LVPECL only)
f_HSDRDPA (LVDS, J=10
LVPECL)
J=8
f_HSCLK (Clock
frequency)
(PCML)
f_HSCLK =
f_HSDR / W
W = 1 to 30
f_HSDR Device
operation
(PCML)
J = 10
J=8
J=7
J=4
J=2
J=1
DPA Run
Length
DPA Jitter
Tolerance_(p-p)
all data rates
DPA Minimum
Eye opening
(p-p)
DPA Receiver
Latency
-5 Speed Grade
Min Typ Max
300
840
300
840
300
840
300
840
100
624
100
462
-6 Speed Grade
Min Typ Max
300
840
300
840
300
840
300
840
100
624
100
462
-7 Speed Grade
Unit
Min Typ Max
300
840 Mbps
300
840 Mbps
300
840 Mbps
300
840 Mbps
100
462 Mbps
100
462 Mbps
300
1000 300
300
1000 300
10
400 10
840 300
840 300
400 10
840 Mbps
840 Mbps
311 MHz
300
400 300
400 300
311 Mbps
300
400 300
400 300
311 Mbps
300
400 300
400 300
311 Mbps
300
400 300
400 300
311 Mbps
100
400 100
400 100
300 Mbps
100
250 100
250 100
200 Mbps
6400
6400
6400 UI
0.44
0.44
0.44 UI
0.56
0.56
0.56
UI
5
9
5
9
5
9 (3)
6–60
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006