EP1SGX10DF672C6 Datasheet, PDF (230/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Timing Model
Table 6–40. M4K Block Internal Timing Microparameter Descriptions
Symbol
t_M4KRC
t_M4KWC
t_M4KWERESU
t_M4KWEREH
t_M4KBESU
t_M4KBEH
t_M4KDATAASU
t_M4KDATAAH
t_M4KADDRASU
t_M4KADDRAH
t_M4KDATABSU
t_M4KDATABH
t_M4KADDRBSU
t_M4KADDRBH
t_M4KDATACO1
t_M4KDATACO2
t_M4KCLKHL
t_M4KCLR
Parameter
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Table 6–41. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
t_{M R A M R C}
t_MRAMWC
t_MRAMWERESU
t_MRAMWEREH
t_MRAMBESU
t_MRAMBEH
t_MRAMDATAASU
t_MRAMDATAAH
t_MRAMADDRASU
t_MRAMADDRAH
Parameter
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
6–28
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006