EP1SGX10DF672C6 Datasheet, PDF (253/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Tables 6–78 and 6–79 show the adder delays for the column and row IOE
programmable delays, respectively. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
Table 6–78. Stratix GX IOE Programmable Delays on Column Pins
Parameter
Setting
Decrease input delay to Off
internal cells
On
Small
Medium
Large
Decrease input delay to Off
input register
On
Decrease input delay to Off
output register
On
Increase delay to output Off
pin
On
Increase delay to output Off
enable pin
On
Increase output clock
Off
enable delay
On
Small
Large
Increase input clock enable Off
delay
On
Small
Large
Increase output enable Off
clock enable delay
On
Small
Large
-5 Speed Grade
Min Max
3,970
3,390
2,810
212
212
3900
0
1,240
0
0
377
0
338
0
540
1,016
1,016
0
540
1,016
1,016
0
540
1,016
1,016
-6 Speed Grade
Min Max
4,367
3,729
3,091
224
224
4,290
0
1,364
0
0
397
0
372
0
594
1,118
1,118
0
594
1,118
1,118
0
594
1,118
1,118
-7 Speed Grade
Unit
Min Max
5,022 ps
4,288 ps
3,554 ps
257
ps
257
ps
4,933 ps
0
ps
1,568 ps
0
ps
0
ps
456
ps
0
ps
427
ps
0
ps
683
ps
1,285 ps
1,285 ps
0
ps
683
ps
1,285 ps
1,285 ps
0
ps
683
ps
1,285 ps
1,285 ps
Altera Corporation
June 2006
6–51
Stratix GX Device Handbook, Volume 1