EP1SGX10DF672C6 Datasheet, PDF (168/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

I/O Structure
Figure 4–63. Stratix GX IOE in Bidirectional I/O Configuration
Column or Row
Interconnect
ioe_clk[7..0]
I/O Interconnect
[15..0]
Note (1)
OE
clkout
ce_out
aclr/prn
Output
Enable Clock
Enable Delay
Output Clock
Enable Delay
Chip-Wide Reset
Logic Array
to Output
Register Delay
sclr/preset
clkin
ce_in
Input Clock
Enable Delay
OE Register
D
Q
ENA
CLRN/PRN
Output
t_ZX Delay
OE Register
t_CO Delay
V_CCIO
Optional
PCI Clamp
V_CCIO
Programmable
Pull-Up
Resistor
Output Register
Output
D
Q _{Pin Delay}
ENA
CLRN/PRN
Drive Strength Control
Open-Drain Output
Slew Control
Input Pin to
Logic Array Delay
Input Register
D
Q
Input Pin to
Input Register Delay
ENA
CLRN/PRN
Bus-Hold
Circuit
Note to Figure 4–63:
(1) All input signals to the IOE can be inverted at the IOE.
The Stratix GX device IOE includes programmable delays that can be
activated to ensure zero hold times, input IOE register-to-logic array
register transfers, or logic array-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
4–102
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005