EP1SGX10DF672C6 Datasheet, PDF (164/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

I/O Structure
Figure 4–59. Row I/O Block Connection to the Interconnect
R4, R8 & R24
Interconnects
C4, C8 & C16
Interconnects
I/O Interconnect
I/O Block Local
Interconnect
16 Control Signals
from I/O Interconnect (1)
16
28 Data & Control
Signals from
Logic Array (2)
LAB
28
Horizontal
I/O Block
io_dataouta[3..0]
io_dataoutb[3..0]
Direct Link
Interconnect
to Adjacent LAB
LAB Local
Interconnect
Direct Link
Interconnect
to Adjacent LAB
io_clk[7:0]
Horizontal I/O
Block Contains
up to Four IOEs
Notes to Figure 4–59:
(1) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_clk[3..0], and four clear signals io_bclr[3..0].
(2) The 28 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables
io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear
signals io_cclr[3..0].
4–98
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005