EP1SGX10DF672C6 Datasheet, PDF (62/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Introduction
The actual lock time for different data patterns varies depending on the
data’s transition density (how often the data switches between 1 and 0)
and jitter characteristic. The DPA circuitry is designed to lock onto any
data pattern with sufficient transition density, so the circuitry works with
current and future protocols. Experiments and simulations show that the
DPA circuitry locks when the data patterns listed in Table 3–4 are
repeated for the specified number of times. There are other suitable
patterns not shown in Table 3–4 and/or pattern lengths, but the lock time
may vary. The circuit can adjust for any phase variation that may occur
during operation.
Table 3–4. Training Patterns for Different Protocols
Protocols
SPI-4, NPSI
RapidIO
Other designs
SFI-4, XSBI
Training Pattern
Ten 0’s, ten 1’s
(00000000001111111111)
Four 0’s, four 1’s (00001111) or one 1,
two 0’s, one 1, four 0’s (10010000)
Eight alternating 1’s and 0’s (10101010 or
01010101)
Not specified
Number of
Repetitions
256
Phase Synchronizer
Each receiver has its own phase synchronizer. The receiver phase
synchronizer aligns the phase of the parallel data from all the receivers to
one global clock. The synchronizers in each channel consist of a 4-bit deep
and J-bit wide FIFO buffer. The parallel clock writes to the FIFO buffer
and the global clock (GCLK) reads from the FIFO buffer. The global and
parallel clock inputs into the synchronizers must have identical
frequencies and differ only in phase. The FIFO buffer never becomes full
or empty (because the source and receive signals are frequency locked)
when operating within the DPA specifications, and the operation does
not require an empty/full flag or read/write enable signals.
Receiver Data Realignment In DPA Mode
While DPA operation aligns the incoming clock phase to the incoming
data phase, it does not guarantee the parallelization boundary or byte
boundary. When the dynamic phase aligner realigns the data bits, the bits
may be shifted out of byte alignment, as shown in Figure 3–10.
3–12
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005