EP1SGX10DF672C6 Datasheet, PDF (206/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Operating Conditions
Table 6–6. Stratix GX Transceiver Block On-Chip Termination (Part 2 of 2)
Symbol
Parameter
Conditions
Min Typ Max Units
Refclkb Dedicated transceiver Commercial and industrial, 100-Ω setting 103 108 113 Ω
clock termination
Commercial and industrial, 120-Ω setting 120 128 134 Ω
Commercial and industrial, 150-Ω setting 149 158 167 Ω
Notes to Tables 6–1 through 6–6:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 6–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns. (The information in this note does not include the
transceiver pins. See note 13 for information about the transient voltage on the transceiver pins.)
(4) Maximum V_CC rise time is 100 ms, and V_CC must rise monotonically.
(5) V_CCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V_CCINT and V_CCIO are
powered.
(7) Typical values are for T_A = 25° C, V_CCINT = 1.5 V, and V_CCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power-up. This applies for all V_CCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(9) Pin pull-up resistance values decrease if an external source drives the pin higher than V_CCIO.
(10) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is
not violated.
(11) Each usable quad requires its own R_REF resistor path to ground. For example, the “D” in the EP1SGX25DC1020
device code means it has two usable quad so two different R_REF pins must be connected to a R_REF resistor each to
ground. The DC signal on the R_REF pin must be as clean as possible. Ensure that no noise is coupled to this pin.
(12) The Stratix GX device’s recommended operating conditions do not include the transceiver. Refer to Tables 6–4 to
6–7.
(13) Minimum DC input to the transceiver pins is –0.5 V. During transitions, the transceiver pins may undershoot to
–0.5 V or overshoot to 3.5 V for input currents less than 100 mA and periods shorter than 20 ns.
Table 6–7. Stratix GX Transceiver Block AC Specification (Part 1 of 7)
Symbol /
Description
Conditions
-5 Commercial
Speed Grade (1)
-6 Commercial &
Industrial Speed
Grade
(1)
-7 Commercial &
Industrial Speed
Grade
Unit
(1)
Power per
quadrant
(PCS +
PMA)
Min Typ Max Min Typ
3.125 Gbps, 400-
450
450
mV V_{o d}
0 pre-emphasis
Max Min Typ Max
mW
6–4
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006