EP1SGX10DF672C6 Datasheet, PDF (110/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

TriMatrix Memory
Figure 4–25. Input/Output Clock Mode in Simple Dual-Port Mode Note (1)
8 LAB Row
Clocks
8
data[ ]
DQ
ENA
Memory Block
Data In
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
address[ ]
DQ
ENA
Read Address
byteena[ ]
DQ
ENA
Data Out
Byte Enable
DQ
ENA
wraddress[ ]
rden
wren
DQ
ENA
DQ
ENA
Write Address
Read Enable
outclken
inclken
wrclock
rdclock
DQ
ENA
Write
Pulse
Generator
Write Enable
Note to Figure 4–25:
(1) All registers shown except the rden register have asynchronous clear ports.
To MultiTrack
Interconnect
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers. Figure 4–26 shows a
memory block in read/write clock mode.
4–44
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005