EP1SGX10DF672C6 Datasheet, PDF (139/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Figure 4–44. EP1SGX40 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Fast Clock Fast Clock Fast Clock Fast Clock
[3]
[2]
[1]
[0]
fclk[1..0]
[4]
[5]
[6]
[7]
Fast Clock Fast Clock Fast Clock Fast Clock
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, 4 regional clock lines, and 2 fast
regional clock lines. Multiplexers are used with these clocks to form 8-bit
busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer at the LAB level selects two of the eight row clocks
to feed the LE registers within the LAB. See Figure 4–45.
Altera Corporation
February 2005
4–73
Stratix GX Device Handbook, Volume 1