EP1SGX10DF672C6 Datasheet, PDF (13/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Transceivers
Each Stratix GX transceiver channel consists of a transmitter and receiver.
The transmitter contains the following:
■ Transmitter PLL
■ Transmitter phase compensation FIFO buffer
■ Byte serializer
■ 8B/10B encoder
■ Serializer (parallel to serial converter)
■ Transmitter output buffer
The receiver contains the following:
■ Input buffer
■ Clock recovery unit (CRU)
■ Deserializer
■ Pattern detector and word aligner
■ Rate matcher and channel aligner
■ 8B/10B decoder
■ Receiver logic array interface
You can set all the Stratix GX transceiver functions through the Quartus II
software. You can set programmable pre-emphasis, programmable
equalizer, and programmable V_OD dynamically as well. Each Stratix GX
transceiver channel is also capable of BIST generation and verification in
addition to various loopback modes. Figure 2–2 shows the block diagram
for the Stratix GX transceiver channel.
Stratix GX transceivers provide physical coding sublayer (PCS) and
physical media attachment (PMA) implementation for protocols such as
10-gigabit XAUI and GIGE. The PCS portion of the transceiver consists of
the logic array interface, 8B/10B encoder/decoder, pattern detector, word
aligner, rate matcher, channel aligner, and the BIST and pseudo-random
binary sequence pattern generator/verifier. The PMA portion of the
transceiver consists of the serializer/deserializer, the CRU, and the I/O
buffers.
Altera Corporation
June 2006
2–3
Stratix GX Device Handbook, Volume 1