EP1SGX10DF672C6 Datasheet, PDF (35/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Transceivers
Receiver State Machine
The receiver state machine operates in GIGE and XAUI modes. In GIGE
mode, the receiver state machine replaces invalid code groups with
9’h1FE. In XAUI mode, the receiver state machine translates the XAUI
PCS code group to the XAUI XGMII code group. Table 2–8 shows the
code conversion. The conversion adheres to the IEEE 802.3ae
specification.
Table 2–8. Code Conversion
XGMII RXC
XGMII RXD
PCS code-group
0
00 through FF
Dxx.y
1
07
K28.0 or K28.3 or K28.5
1
07
K28.5
1
9C
K28.4
1
FB
K27.7
1
FD
K29.7
1
FE
K30.7
1
FE
Invalid code group
1
See IEEE 802.3 reserved code See IEEE 802.3 reserved
groups
code groups
Description
Normal Data
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Invalid XGMII character
Reserved code groups
Byte Deserializer
The byte deserializer takes a single width word (8 or 10 bits) from the
transceiver logic and converts it into double-width words (16 or 20 bits)
to the phase compensation FIFO buffer. The byte deserializer is bypassed
when single width mode (8 or 10 bits) is used at the PLD interface.
Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer resides in the transceiver
block at the programmable logic device (PLD) boundary. This buffer
compensates for the phase difference between the recovered clock within
the transceiver and the recovered clock after it has transferred to the PLD
core. The phase compensation FIFO buffer is four words deep and cannot
be bypassed.
Altera Corporation
June 2006
2–25
Stratix GX Device Handbook, Volume 1