EP1SGX10DF672C6 Datasheet, PDF (159/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
unless the PLL is using external feedback mode. In order to lock in
external feedback mode, the external output must drive the board trace
back to the FBIN pin.
Figure 4–56. extclkena Signals
COUNTER
OUTPUT
CLKENA
CLKOUT
Fast PLLs
Stratix GX devices contain up to four fast PLLs with high-speed serial
interfacing ability, along with general-purpose features. Figure 4–57
shows a diagram of the fast PLL.
Altera Corporation
February 2005
4–93
Stratix GX Device Handbook, Volume 1