EP1SGX10DF672C6 Datasheet, PDF (108/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

TriMatrix Memory
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers. Figures 4–24 and 4–25 show the memory block in input/output
clock mode.
4–42
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005