EP1SGX10DF672C6 Datasheet, PDF (43/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Transceivers
The receiver PLL can also drive the fast regional, regional clocks, and
local routing adjacent to the associated transceiver block. Figures 2–28
through 2–31 show which fast regional and regional clock resource can be
used by the recovered clock.
In the EP1SGX25 device, the receiver PLL recovered clocks from
transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2
and 3 drive RCLK[7..6]. The regional clocks feed logic in their
associated regions.
Figure 2–28. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock
Connection
Stratix GX
PLD
Transceiver Blocks
Block 0
RCLK[11..10]
Block 1
Block 2
RCLK[9..8]
Block 3
In addition, the receiver PLL’s recovered clocks can drive fast regional
lines (FCLK) as shown Figure 2–29. The fast regional clocks can feed logic
in their associated regions.
Altera Corporation
June 2006
2–33
Stratix GX Device Handbook, Volume 1