EP1SGX10DF672C6 Datasheet, PDF (69/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [7..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack^TM interconnect’s inherent low skew
allows clock and control signal distribution in addition to data. Figure 4–3
shows the LAB control signal generation circuit.
Figure 4–3. LAB-Wide Control Signals
Dedicated
8
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk1
labclk2
asyncload
or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Stratix GX architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 4–4.
Altera Corporation
February 2005
4–3
Stratix GX Device Handbook, Volume 1