EP1SGX10DF672C6 Datasheet, PDF (57/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Source-Synchronous Signaling With DPA
have four dedicated fast PLLs for clock multiplication. Table 3–3 shows
the maximum number of channels in each Stratix GX device that support
DPA.
Table 3–3. Stratix GX Source-Synchronous Differential I/O Resources
Device
EP1SGX10C
EP1SGX10D
EP1SGX25C
EP1SGX25D
EP1SGX25F
EP1SGX40D
EP1SGX40G
Fast PLLs
2 (3)
2 (3)
2
2
2
4 (4)
4 (4)
Pin Count
672
672
672
672
1,020
1,020
1,020
1,020
Receiver
Channels
(1)
Transmitter
Channels
(1)
22
22
22
22
39
39
39
39
39
39
39
39
45
45
45
45
Receiver &
Transmitter
Channel Speed
(Gbps) (2)
1
1
1
1
1
1
1
1
LEs
10,570
10,570
25,660
25,660
25,660
25,660
41,250
41,250
Notes to Table 3–3:
(1) This is the number of receiver or transmitter channels in the source-synchronous (I/O bank 1 and 2) interface of
the device.
(2) Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mbps.
(3) One of the two fast PLLs in EP1SGX10C and EP1SGX10D devices supports DPA.
(4) Two of the four fast PLLs in EP1SGX40D and EP1SGX40G devices support DPA
The receiver and transmitter channels are interleaved so that each I/O
row in I/O banks 1 and 2 of the device has one receiver channel and one
transmitter channel per row. Figures 3–6 and 3–7 show the fast PLL and
channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40
devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations.
Altera Corporation
August 2005
3–7
Stratix GX Device Handbook, Volume 1