EP1SGX10DF672C6 Datasheet, PDF (207/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–7. Stratix GX Transceiver Block AC Specification (Part 2 of 7)
Symbol /
Description
Conditions
-5 Commercial
Speed Grade (1)
-6 Commercial &
Industrial Speed
Grade
(1)
-7 Commercial &
Industrial Speed
Grade
Unit
(1)
Min Typ Max Min Typ Max Min Typ Max
Reference Clock
Jitter
tolerance
(peak-to-
peak)
Jitter
components
<20 MHz
Wideband
Reference Dedicated
25
input clock refclkb pins
frequency _{PLD clock}
25
resources
Receiver
Serial data Commercial /
614
rate
industrial
(general)
Serial data Commercial /
500
rate (8B/10B industrial
encoded)
Parallel
20
transceiver/
logic array
interface
speed
Rate
matching
frequency
tolerance
XAUI mode only
20
50
650 25
325 25
3,187.5 614
3,187.5 500
398.4 20
±100
20
50
650 25
325 25
20
ps
50
ps
312.5 MHz
156.25 MHz
3,187.5 614
3,187.5 500
375 20
2,500 Mbps
2,500 Mbps
312.5 MHz
±100
±100 ppm
8B/10B Custom Receiver Jitter Tolerance using Encoded CJPAT Note (2)
Deterministic 500 Mbps
jitter
Total jitter 500 Mbps
0.45
0.45
0.71
0.71
Fibre Channel Receiver Jitter Tolerance using 8B/10B Encoded CJTPAT Note (2)
Deterministic 1.0625 Gbps
jitter
Total jitter 1.0625 Gbps
0.37
0.37
0.68
0.68
0.45 UI
0.71 UI
0.37 UI
0.68 UI
Altera Corporation
June 2006
6–5
Stratix GX Device Handbook, Volume 1