EP1SGX10DF672C6 Datasheet, PDF (75/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
for accumulator functions. Another portion of the LUT generates carry-
out bits. An LAB-wide carry in bit selects which chain to use for the
addition of given inputs. The carry-in signal for each chain, carry-in0
or carry-in1, selects the carry-out to carry forward to the carry-in
signal of the next-higher-order bit. The final carry-out signal is routed to
an LE, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain runs vertically allowing fast horizontal connections to TriMatrix^™
memory and DSP blocks. A carry chain can continue as far as a full
column.
Altera Corporation
February 2005
4–9
Stratix GX Device Handbook, Volume 1