EP1SGX10DF672C6 Datasheet, PDF (250/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Timing Model
Table 6–75. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
Standard
2.5-V LVTTL
2 mA
8 mA
12 mA
16 mA
1.8-V LVTTL
2 mA
8 mA
12 mA
1.5-V LVTTL
2 mA
4 mA
8 mA
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS (1)
LVPECL (1)
PCML (1)
HyperTransport Technology (1)
-5 Speed Grade
Min
Max
830
250
140
100
1,510
420
350
1,740
1,160
690
50
90
–50
100
20
–20
40
–60
70
-6 Speed Grade
Min
Max
872
263
147
105
1,586
441
368
1,827
1,218
725
53
95
–52
105
21
–21
42
–63
74
-7 Speed Grade
Unit
Min
Max
1,002
ps
302
ps
169
ps
120
ps
1,824
ps
507
ps
423
ps
2,101
ps
1,400
ps
833
ps
61
ps
109
ps
–60
ps
120
ps
24
ps
–24
ps
48
ps
–73
ps
85
ps
Table 6–76. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
I/O Standard
LVCMOS
2 mA
4 mA
8 mA
12 mA
24 mA
-5 Speed Grade
Min
Max
1,911
1,911
1,691
1,471
1,341
-6 Speed Grade
Min
Max
2,011
2,011
1,780
1,549
1,412
-7 Speed Grade
Unit
Min
Max
2,312
ps
2,312
ps
2,046
ps
1,780
ps
1,623
ps
6–48
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006