|
EP1SGX10DF672C6 Datasheet, PDF (246/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet | |||
|
◁ |
Timing Model
Table 6â71. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2)
Symbol
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.000
5.365
2.000
5.775
2.000
6.621
ns
1.126
1.186
1.352
ns
0.000
0.000
0.000
ns
0.500
2.304
0.500
2.427
0.500
2.765
ns
External I/O Delay Parameters
External I/O delay timing parameters, both for I/O standard input and
output adders and programmable input and output delays, are specified
by speed grade, independent of device density.
Tables 6â72 through 6â77 show the adder delays associated with column
and row I/O pins. If an I/O standard is selected other than LVTTL 24 mA
with a fast slew rate, add the selected delay to the external tCO and tSU I/O
parameters.
Table 6â72. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
I/O Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1Ã
AGP 2Ã
CTT
SSTL-3 class I
SSTL-3 class II
-5 Speed Grade
Min
Max
0
0
30
150
210
220
220
0
0
0
0
0
120
â30
â30
-6 Speed Grade
Min
Max
0
0
31
157
220
231
231
0
0
0
0
0
126
â32
â32
-7 Speed Grade
Unit
Min
Max
0
ps
0
ps
35
ps
180
ps
252
ps
265
ps
265
ps
0
ps
0
ps
0
ps
0
ps
0
ps
144
ps
â37
ps
â37
ps
6â44
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
|
▷ |