EP1SGX10DF672C6 Datasheet, PDF (145/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 4–48. PLL Floorplan
FPLL7CLK 7
CLK[15..12]
5 11
Stratix GX Architecture
High-Speed
Transceivers
inclk1
1
CLK[3..0]
2
PLLs
FPLL8CLK 8
inclk2
inclk3
inclk4
inclk5
6 12
CLK[7..4]
Figure 4–49 shows the global and regional clock connections from the
PLL outputs and the CLK pins.
Altera Corporation
February 2005
4–79
Stratix GX Device Handbook, Volume 1