EP1SGX10DF672C6 Datasheet, PDF (232/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Timing Model
Table 6–43. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 2 of 2)
Symbol
Parameter
t_{R X _ F R E Q L O C K}
The time until the clock recovery unit (CRU)
switches to data mode from lock to reference
mode.
t_{R X _ F R E Q L O C K 2 P H A S E L O C K} The time until CRU phase locks to data after
switching from lock to data mode.
Figure 6–4 shows the TriMatrix memory waveforms for the M512, M4K,
and M-RAM timing parameters shown in Tables 6–39 through 6–41.
Figure 6–4. Dual-Port RAM Timing Microparameter Waveform
wrclock
tWEREH
wren
wraddress
data-in
rdclock
rden
rdaddress
reg_data-out
unreg_data-out
an-1
an
a0
din-1
tDATAH
din
tDATASU
tWERESU
bn
doutn-2
doutn-1
b0
doutn-1
doutn
a1
a2
tWEREH
tRC
b1
tDATACO1
doutn
tDATACO2
dout0
tWERESU
tWADDRSU
a3
tWADDRH
a4
a5
din4
din5
a6
din6
b2
b3
dout0
6–30
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006