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EP1SGX10DF672C6 Datasheet, PDF (190/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet | |||
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 4â35. 32-Bit Stratix GX Device IDCODE (Part 2 of 2)
Device
Version (4 Bits)
EP1SGX40
0000
IDCODE (32 Bits) (1)
Part Number (16 Bits)
Manufacturer Identity
(11 Bits)
0010 0000 0100 0101
000 0110 1110
LSB (1 Bit) (2)
1
Notes to Table 4â35:
(1) The most significant bit (MSB) is at the left end of the string.
(2) The IDCODEâs least significant bit (LSB) is always 1.
Figure 4â72 shows the timing requirements for the JTAG signals.
Figure 4â72. Stratix GX JTAG Waveforms
TMS
TDI
TCK
TDO
Signal
to Be
Captured
Signal
to Be
Driven
t JCP
t JCH
t JCL
t JPSU
tJPZX
tJSSU
tJPCO
tJSH
tJSZX
tJSCO
t JPH
t JPXZ
tJSXZ
Table 4â36 shows the JTAG timing parameters and values for Stratix GX
devices.
Table 4â36. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2)
Symbol
Parameter
tJ C P
tJ C H
tJ C L
tJ P S U
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
Min (ns) Max (ns)
100
50
50
20
4â124
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005
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