EP1SGX10DF672C6 Datasheet, PDF (247/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–72. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 2 of 2)
I/O Standard
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
-5 Speed Grade
Min
Max
–70
–70
180
180
120
120
70
70
-6 Speed Grade
Min
Max
–74
–74
189
189
126
126
73
73
-7 Speed Grade
Unit
Min
Max
–86
ps
–86
ps
217
ps
217
ps
144
ps
144
ps
83
ps
83
ps
Table 6–73. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 1 of 2)
I/O Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
-5 Speed Grade
Min
Max
0
0
30
150
210
0
220
0
0
0
0
0
80
–30
–30
–70
–70
180
0
130
-6 Speed Grade
Min
Max
0
0
31
157
220
0
231
0
0
0
0
0
84
–32
–32
–74
–74
189
0
136
-7 Speed Grade
Unit
Min
Max
0
ps
0
ps
35
ps
180
ps
252
ps
0
ps
265
ps
0
ps
0
ps
0
ps
0
ps
0
ps
96
ps
–37
ps
–37
ps
–86
ps
–86
ps
217
ps
0
ps
156
ps
Altera Corporation
June 2006
6–45
Stratix GX Device Handbook, Volume 1