EP1SGX10DF672C6 Datasheet, PDF (56/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Introduction
Unlike the de-skew function in APEX^TM 20KE and APEX 20KC devices,
you do not have to use a fixed training pattern with DPA in Stratix GX
devices. Table 3–1 shows the differences between source-synchronous
circuitry with DPA and source-synchronous circuitry without DPA
circuitry in Stratix GX devices.
Table 3–1. Source-Synchronous Circuitry With & Without DPA
Feature
Data rate
Deserialization factors
Clock frequency
Interface pins
Receiver pins
Source-Synchronous Circuitry
Without DPA
With DPA
300 to 840 Megabits per 300 Mbps to 1 Gbps
second (Mbps)
1, 2, 4, 8, 10
8, 10
10 to 717 MHz
74 to 717 MHz
I/O banks 1 and 2
I/O banks 1 and 2
Dedicated inputs
Dedicated inputs
DPA Input Support
Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to
support differential I/O standards at speeds up to 1 Gbps with DPA (or
up to 840 Mbps without DPA). Stratix GX device source-synchronous
circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards, each
with a supply voltage of 3.3 V. Refer to the High-Speed Source-Synchronous
Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX
Device Handbook, Volume 2 for more information on these I/O standards.
Transmitter pins can be either input or output pins for single-ended I/O
standards. Refer to Table 3–2.
Table 3–2. Bank 1 & 2 Input Pins
Input Pin Type
Differential
Single ended
I/O Standard
Differential
Single ended
Receiver Pin
Input only
Input only
Transmitter Pin
Output only
Input or output
Interface & Fast PLL
This section describes the number of channels that support DPA and their
relationship with the PLL in Stratix GX devices. EP1SGX10 and
EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices
3–6
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005