EP1SGX10DF672C6 Datasheet, PDF (26/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 2–13. Receiver PLL & CRU Circuit
Receiver PLL
÷ m (1)
Low-Speed TX_PLL_CLK
Inter Transceiver Routing (IQ2)
Global Clks, IO Bus, Gen Routing
RX CRUCLK
rx_locked
PFD
up
down
up
down
Charge Pump
and Loop Filter
VCO
Dedicated
Local
÷2
REFCLKB
Note to Figure 2–13:
(1) m = 8, 10 16, or 20.
rx_locktorefclk
rx_locktodata
RX_IN
CRU
rx_freqlocked[]
rx_riv[ ]
High-speed RCVD_CLK
Low-speed RCVD_CLK
The receiver PLLs and CRUs are capable of supporting up to 3.1875 Gbps.
The input clock frequency for –5 and –6 speed grade devices is limited to
650 MHz if you use the REFCLKB pin or 325 MHz if you use the other
clock routing resources. The maximum input clock frequency for –7 speed
grade devices is 312.5 MHz if you use the REFCLKB pin or 156.25 MHz
with the other clock routing resources. An optional RX_LOCKED port
(active low signal) is available to indicate whether the PLL is locked to the
reference clock. The receiver PLL has a programmable loop bandwidth,
which can be set to low, medium, or high. The loop bandwidth parameter
can be statically set by the Quartus II software.
Table 2–5 lists the adjustable parameters of the receiver PLL and CRU. All
the parameters listed are statically programmable in the Quartus II
software.
Table 2–5. Receiver PLL & CRU Adjustable Parameters (Part 1 of 2)
Parameter
Input reference frequency range
Data rate support
Specifications
25 MHz to 650 MHz
500 Mbps to 3.1875 Gbps
2–16
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006