EP1SGX10DF672C6 Datasheet, PDF (265/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Symbol
t_OUTDUTY
t_JITTER
t_CONFIG5,6
t_CONFIG11,12
t_SCANCLK
t_DLOCK
t_LOCK
f_VCO
t_LSKEW
t_SKEW
f_SS
% spread
t_ARESET
Parameter
Min Typ
Duty cycle for external clock output
45
(when set to 50%)
Period jitter for external clock output (5)
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency (4)
Time required to lock dynamically (after
switchover or reconfiguring any non-
post-scale counters/delays) (6)
Time required to lock from end of
10
device configuration
PLL internal VCO operating range
300
Clock skew between two external clock
±50
outputs driven by the same counter
Clock skew between two external clock
±75
outputs driven by the different counters
with the same settings
Spread spectrum modulation frequency 30
Percentage spread for spread
spectrum frequency (9)
0.4 0.5
Minimum pulse width on areset
10
signal
Max
55
±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
289/f_SCANCLK
193/f_SCANCLK
22
100
400
800 (7)
150
0.6
Unit
%
ps or
mUI
MHz
μs
μs
MHz
ps
ps
kHz
%
ns
Table 6–89. Enhanced PLL Specifications for -6 Speed Grades (Part 1 of 2)
Symbol
f_IN
f_INDUTY
f_EINDUTY
t_INJITTER
t_EINJITTER
t_FCOMP
Parameter
Min Typ
Input clock frequency
3 (1)
Input clock duty cycle
40
External feedback clock input duty
40
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time (3)
Max
650
60
60
±200 (2)
±200 (2)
6
Unit
MHz
%
%
ps
ps
ns
Altera Corporation
June 2006
6–63
Stratix GX Device Handbook, Volume 1