EP1SGX10DF672C6 Datasheet, PDF (111/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Figure 4–26. Read/Write Clock Mode in Simple Dual-Port Mode Note (1)
8 LAB Row
Clocks
8
data[ ]
DQ
ENA
Memory Block
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
4,096 × 1
address[ ]
DQ
ENA
Data Out
Read Address
DQ
ENA
wraddress[ ]
DQ
ENA
Write Address
byteena[ ]
rden
wren
DQ
ENA
DQ
ENA
Byte Enable
Read Enable
outclken
inclken
wrclock
rdclock
DQ
ENA
Write
Pulse
Generator
Write Enable
Note to Figure 4–26:
(1) All registers shown except the rden register have asynchronous clear ports.
To MultiTrack
Interconnect
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See Figure 4–27. A single
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block is less than or equal to
2K bits in size.
Altera Corporation
February 2005
4–45
Stratix GX Device Handbook, Volume 1