EP1SGX10DF672C6 Datasheet, PDF (257/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–82. Stratix GX Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[8..7]CLK Pins
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422
422
390
422
422
390
422
422
390
422
422
390
422
422
390
300
250
200
300
250
200
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
422
422
390
422
422
390
422
422
390
422
422
390
422
422
390
300
250
200
400
350
300
717
717
640
717
717
640
400
375
350
717
717
640
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 6–83. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 1 of 2)
LVTTL
2.5 V
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade Unit
422
422
390
MHz
422
422
390
MHz
Altera Corporation
June 2006
6–55
Stratix GX Device Handbook, Volume 1