EP1SGX10DF672C6 Datasheet, PDF (173/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Figure 4–67. Output Timing Diagram in DDR Mode
CLK
A
From Internal
Registers
B
A1
A2
A3
A4
B1
B2
B3
B4
DDR output
B1 A1 B2 A2 B3 A3
The Stratix GX IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. Stratix GX device I/O pins
transfer data on a DDR bidirectional bus to support DDR SDRAM. The
negative-edge-clocked OE register holds the OE signal inactive until the
falling edge of the clock. This is done to meet DDR SDRAM timing
requirements.
f
External RAM Interfacing
Stratix GX devices support DDR SDRAM at up to 200 MHz (400-Mbps
data rate) through dedicated phase-shift circuitry, QDR and QDRII
SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200
MHz. Stratix GX devices also provide preliminary support for reduced
latency DRAM II (RLDRAM II) at rates up to 200 MHz through the
dedicated phase-shift circuitry.
1 In addition to the required signals for external memory
interfacing, Stratix GX devices offer the optional clock enable
signal. By default the Quartus II software sets the clock enable
signal high, which tells the output register to update with new
values. The output registers hold their own values if the design
sets the clock enable signal low. See Figure 4–63.
To find out more about the DDR SDRAM specification, see the JEDEC
web site (www.jedec.org). For information on memory controller
megafunctions for Stratix GX devices, see the Altera web site
(www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix &
Stratix GX Devices for more information on DDR SDRAM interface in
Stratix GX. Also see AN 349: QDR SRAM Controller Reference Design for
Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices.
Altera Corporation
February 2005
4–107
Stratix GX Device Handbook, Volume 1