EP1SGX10DF672C6 Datasheet, PDF (263/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–87. High-Speed I/O Specifications (Part 3 of 4) Notes (1), (2)
Symbol
Conditions
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
DPA Lock Time
Standard
Train
ing
Patt
ern
Trans
ition
Den-
sity
SPI-4, 0000 10% 256
256
256
(4)
CSIX 0000
0011
1111
1111
Rapid IO 0000 25% 256
256
256
(4)
1111
1001 50% 256
256
256
(4)
0000
Misc
1010 100 256
256
256
(4)
1010 %
0101
256
256
256
(4)
0101
TCCS
All
200
200
300 ps
SW
PCML (J = 4, 7, 8, 10) 750
750
800
ps
PCML (J = 2)
900
900
1,200
ps
PCML (J = 1)
1,500
1,500
1,700
ps
LVDS and LVPECL
500
500
550
ps
(J = 1)
LVDS, LVPECL,
440
440
500
ps
HyperTransport
technology (J = 2
through 10)
Input jitter
All
tolerance
(peak-to-peak)
250
250
250 ps
Output jitter
All
(peak-to-peak)
160
160
200 ps
Output t_RISE
LVDS
HyperTransport
technology
80 110 120 80 110 120 80 110 120 ps
110 170 200 110 170 200 120 170 200 ps
LVPECL
90 130 150 90 130 150 100 135 150 ps
PCML
80 110 135 80 110 135 80 110 135 ps
Altera Corporation
June 2006
6–61
Stratix GX Device Handbook, Volume 1