EP1SGX10DF672C6 Datasheet, PDF (266/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

High-Speed I/O Specification
Table 6–89. Enhanced PLL Specifications for -6 Speed Grades (Part 2 of 2)
Symbol
f_OUT
f_{OUT_EXT}
t_OUTDUTY
t_JITTER
t_CONFIG5,6
t_CONFIG11,12
t_SCANCLK
t_DLOCK
t_LOCK
f_VCO
t_LSKEW
t_SKEW
f_SS
% spread
t_ARESET
Parameter
Min Typ
Output frequency for internal global or 0.3
regional clock
Output frequency for external clock (2) 0.3
Duty cycle for external clock output
45
(when set to 50%)
Period jitter for external clock output (5)
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency (4)
Time required to lock dynamically (after (8)
switchover or reconfiguring any non-
post-scale counters/delays) (6) (10)
Time required to lock from end of
10
device configuration (10)
PLL internal VCO operating range
300
Clock skew between two external clock
±50
outputs driven by the same counter
Clock skew between two external clock
±75
outputs driven by the different counters
with the same settings
Spread spectrum modulation frequency 30
Percentage spread for spread
spectrum frequency (9)
0.4 0.5
Minimum pulse width on areset
10
signal
Max
450
500
55
±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
289/f_SCANCLK
193/f_SCANCLK
22
100
400
800 (7)
150
0.6
Unit
MHz
MHz
%
ps or
mUI
MHz
μs
μs
MHz
ps
ps
kHz
%
ns
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 3)
Symbol
f_IN
f_INDUTY
f_EINDUTY
t_INJITTER
t_EINJITTER
Parameter
Input clock frequency
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
External feedback clock period jitter
Min Typ
3 (1)
40
40
Max
565
60
60
±200 (2)
±200 (2)
Unit
MHz
%
%
ps
ps
6–64
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006