EP1SGX10DF672C6 Datasheet, PDF (270/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DLL Jitter
Table 6–92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 2 of 2)
Symbol
t_DUTY
t_JITTER
t_LOCK
m
l0, l1, g0
t_ARESET
Parameter
Min
Max
Unit
Duty cycle for DFFIO 1× CLKOUT pin (3) 45
55
%
Period jitter for DIFFIO clock out (3)
±80
ps
Period jitter for internal global or
regional clock
±100 ps for >200 MHz outclk ps or
±20 mUI for <200 MHz outclk mUI
Time required for PLL to acquire lock 10
100
μs
Multiplication factors for m counter (4) 1
32
Integer
Multiplication factors for l0, l1, and g0
1
counter (4), (5)
32
Integer
Minimum pulse width on areset
10
ns
signal
Notes to Tables 6–91 & 6–92:
(1) See “Maximum Input & Output Clock Rates” on page 6–54.
(2) When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
(3) This parameter is for high-speed differential I/O mode only.
(4) These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
(5) High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
DLL Jitter
Table 6–93 reports the jitter for the DLL in the DQS phase-shift reference
circuit.
Table 6–93. DLL Jitter for DQS Phase Shift Reference Circuit
Frequency (MHz)
197 to 200
160 to 196
100 to 159
± 100
± 300
± 500
DLL Jitter (ps)
6–68
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006