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EP1SGX10DF672C6 Datasheet, PDF (260/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet | |||
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High-Speed I/O Specification
Table 6â85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 2 of 2)
I/O Standard
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
HSTL class I
HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1Ã
AGP 2Ã
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
350
300
300
400
350
300
200
167
125
200
167
125
167
150
133
167
150
133
150
133
133
150
133
133
150
133
133
150
133
133
250
225
200
225
225
200
250
225
200
225
225
200
400
350
300
400
350
300
400
350
300
300
250
200
225
225
200
717
717
500
717
717
500
420
420
420
420
420
420
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
High-Speed I/O
Specification
Table 6â86 provides high-speed timing specifications definitions.
Table 6â86. High-Speed Timing Specifications & Definitions (Part 1 of 2)
High-Speed Timing Specification
tC
fHSCLK
tRISE
Definitions
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
6â58
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
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