EP1SGX10DF672C6 Datasheet, PDF (259/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–84. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 2 of 2)
I/O Standard
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
Differential SSTL-2
LVDS
LVPECL
PCML
HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
250
250
250
225
200
200
350
300
250
200
167
125
200
167
125
167
150
133
167
150
133
200
200
167
200
200
167
150
133
133
150
133
133
250
225
200
225
200
200
250
225
200
225
200
200
350
300
250
350
300
250
350
300
250
350
300
250
350
300
250
200
200
200
225
200
200
200
200
167
500
500
500
500
500
500
350
350
350
350
350
350
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 6–85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 1 of 2)
LVTTL
2.5 V
1.8 V
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade Unit
400
350
300
MHz
400
350
300
MHz
400
350
300
MHz
Altera Corporation
June 2006
6–57
Stratix GX Device Handbook, Volume 1