EP1SGX10DF672C6 Datasheet, PDF (115/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Table 4–12 shows the number of DSP blocks in each Stratix GX device.
Table 4–12. DSP Blocks in Stratix GX Devices Notes (1), (2)
Device
EP1SGX10
EP1SGX25
EP1SGX40
DSP Blocks
6
10
14
Total 9 × 9
Multipliers
48
80
112
Total 18 × 18 Total 36 × 36
Multipliers Multipliers
24
6
40
10
56
14
Notes to Table 4–12:
(1) Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
(2) The number of supported multiply functions shown is based on signed/signed
or unsigned/unsigned implementations.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator within the block depending on the configuration. This
makes routing to LEs easier, saves LE routing resources, and increases
performance, because all connections and blocks are within the DSP
block. Additionally, the DSP block input registers can efficiently
implement shift registers for FIR filter applications.
Figure 4–29 shows the top-level diagram of the DSP block configured for
18 × 18-bit multiplier mode. Figure 4–30 shows the 9 × 9-bit multiplier
configuration of the DSP block.
Altera Corporation
February 2005
4–49
Stratix GX Device Handbook, Volume 1