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EP1SGX10DF672C6 Datasheet, PDF (238/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet | |||
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Timing Model
Figure 6â6. External Timing in Stratix GX Devices
Dedicated
Clock
OE Register
PRN
DQ
CLRN
Output Register
PRN
DQ
CLRN
Input Register
PRN
DQ
CLRN
tINSU
tINH
tOUTCO
Bidirectional
Pin
All external I/O timing parameters shown are for 3.3-V LVTTL or
LVCMOS I/O standards with the maximum current strength. For
external I/O timing using standards other than LVTTL or LVCMOS use
the I/O standard input and output delay adders in Tables 6â72 through
6â76.
Table 6â51 shows the external I/O timing parameters when using fast
regional clock networks.
Table 6â51. Stratix GX Fast Regional Clock External I/O Timing Parameters Notes (1), (2)
Symbol
tINSU
tINH
tOUTCO
Parameter
Setup time for input or bidirectional pin using column IOE
input register with fast regional clock fed by FCLK pin
Hold time for input or bidirectional pin using column IOE
input register with fast regional clock fed by FCLK pin
Clock-to-output delay output or bidirectional pin using
column IOE output register with fast regional clock fed by
FCLK pin
Conditions
CL O A D = 10 pF
Notes to Table 6â51:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device
and speed grade and whether it is tCO or tSU. You should use the Quartus II software to verify the external timing
for any pin.
6â36
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
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