EP1SGX10DF672C6 Datasheet, PDF (151/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
f
requiring a system-controlled switchover between frequencies of
operation. You can use clkswitch together with the lock signal to
trigger the switch from a clock that is running but becomes unstable
and cannot be locked onto.
During switchover, the PLL VCO continues to run and either slows down
or speeds up, generating frequency drift on the PLL outputs. The clock
switchover transitions without any glitches. After the switch, there is a
finite resynchronization period to lock onto new clock as the VCO ramps
up. The exact amount of time it takes for the PLL to relock relates to the
PLL configuration and may be adjusted by using the programmable
bandwidth feature of the PLL. The preliminary specification for the
maximum time to relock is 100 µs.
For more information on clock switchover, see AN313: Implementing
Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change
Stratix GX device enhanced PLL counters and delay elements without
reloading a Programmer Object File (.pof). This provides considerable
flexibility for frequency synthesis, allowing real-time PLL frequency and
output clock delay variation. You can sweep the PLL output frequencies
and clock delay in prototype environments. The PLL reconfiguration
feature can also dynamically or intelligently control system clock speeds
or t_CO delays in end systems.
Clock delay elements at each PLL output port implement variable delay.
Figure 4–53 shows a diagram of the overall dynamic PLL control feature
for the counters and the clock delay elements. The configuration time is
less than 20 μs for the enhanced PLL using a input shift clock rate of
25 MHz. The charge pump, loop filter components, and phase shifting
using VCO phase taps cannot be dynamically adjusted.
Altera Corporation
February 2005
4–85
Stratix GX Device Handbook, Volume 1