EP1SGX10DF672C6 Datasheet, PDF (191/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Table 4–36. Stratix GX JTAG Timing Parameters & Values (Part 2 of 2)
Symbol
Parameter
Min (ns) Max (ns)
t_{J P H}
JTAG port hold time
45
t_{J P C O} JTAG port clock to output
25
t_{J P Z X}
JTAG port high impedance to valid output
25
t_{J P X Z}
JTAG port valid output to high impedance
25
t_{J S S U} Capture register setup time
20
t_{J S H}
Capture register hold time
45
t_{J S C O} Update register clock to output
35
t_{J S Z X}
Update register high impedance to valid output
35
t_{J S X Z}
Update register valid output to high impedance
35
Altera Corporation
February 2005
4–125
Stratix GX Device Handbook, Volume 1