EP1SGX10DF672C6 Datasheet, PDF (46/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 2–31. EP1SGX40 Receiver PLL Recovered Clock to Fast Regional Clock
Connection
PLD
Stratix GX
FCLK[1..0] Transceiver Blocks
Block 0
Block 1
Block 4
Block 2
Block 3
FCLK[1..0]
Table 2–10 summarizes the possible clocking connections for the
transceivers.
Table 2–10. Possible Clocking Connections for Transceivers (Part 1 of 2)
Source
REFCLKB
Transmitter PLL
Receiver PLL
GCLK
RCLK
FCLK
Transmitter
PLL
v
v
v
v
Receiver
PLL
v
v
v
v
v
Destination
GCLK
v (1)
v
v
RCLK
v
v
v
FCLK
v
v
IQ Lines
v (1)
2–36
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006