EP1SGX10DF672C6 Datasheet, PDF (45/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Transceivers
Figure 2–30. EP1SGX40 Receiver PLL Recovered Clock to Regional Clock
Connection
Stratix GX
PLD
Transceiver Blocks
Block 0
RCLK[11..10]
Block 1
Block 4
Block 2
RCLK[9..8]
Block 3
Figure 2–31 shows the possible recovered clock connection to the fast
regional clock resource. The fast regional clocks can drive logic in their
associated regions.
Altera Corporation
June 2006
2–35
Stratix GX Device Handbook, Volume 1