EP1SGX10DF672C6 Datasheet, PDF (148/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

PLLs & Clock Networks
Enhanced PLLs
Stratix GX devices contain up to four enhanced PLLs with advanced
clock management features. Figure 4–51 shows a diagram of the
enhanced PLL.
Figure 4–51. Stratix GX Enhanced PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
From Adjacent PLL
Post-Scale
Counters
Programmable
Time Delay on
Each PLL Port
/l0
Δt
CLK0
CLK1
Clock
Switch-Over
Circuitry
Phase Frequency
Detector
Spread
Spectrum
/n
Δt
PFD
Charge
Pump
Loop
Filter
8
VCO
/l1
Δt
4
/g0
Δt
/g1
Δt
(1)
FBIN
Δt
/m
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
/g2
Δt
/g3
Δt
/e0
Δt
/e1
Δt
4
/e2
Δt
/e3
Δt
Regional
Clocks
Global
Clocks
I/O Buffers ₍₂₎
to I/O or general
routing
I/O Buffers (3)
Notes to Figure 4–51:
(1) External feedback is available in PLLs 5 and 6.
(2) This external output is available from the g0 counter for PLLs 11 and 12.
(3) These counters and external outputs are available in PLLs 5 and 6.
4–82
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005