EP1SGX10DF672C6 Datasheet, PDF (70/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Logic Elements
Figure 4–4. Stratix GX LE
addnsub
LAB Carry-In
Carry-In1
Carry-In0
Register chain
routing from
previous LE
LAB-wide
Synchronous
Load
LAB-wide
Synchronous
Clear
Register Bypass
Packed
Register Select
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry
Chain
Synchronous
Load and
Clear Logic
PRN/ALD
D
Q
ADATA
ENA
CLRN
labclr1
labclr2
labpre/aload
Chip-Wide
Reset
labclk1
labclk2
labclkena1
labclkena2
Asynchronous
Clear/Preset/
Load Logic
Clock &
Clock Enable
Select
Carry-Out0
Carry-Out1
LAB Carry-Out
Register
Feedback
Programmable
Register
LUT chain
routing to next LE
Row, column,
and direct link
routing
Row, column,
and direct link
routing
Local Routing
Register chain
output
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register’s
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3 input of the LE. For combinatorial functions, the register is
bypassed and the output of the LUT drives directly to the outputs of the
LE.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
functions. Another special packing mode allows the register output to
feed back into the LUT of the same LE so that the register is packed with
4–4
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005