EP1SGX10DF672C6 Datasheet, PDF (42/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 2–27. EP1SGX40G Device Inter-Transceiver & Global Clock Connections Note (1)
Transceiver Block 0
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
refclkb
/2
IQ2
Global Clks, I/O Bus, Gen Routing
TX PLL
4
4
Receiver
PLLs
IQ0 IQ1 IQ2
Transceiver Block 1
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
refclkb
/2
IQ2
Global Clks, I/O Bus, Gen Routing
TX PLL
4
Receiver
PLLs
(2)
4
Transceiver Block 4
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
refclkb
/2
IQ2
Global Clks, I/O Bus, Gen Routing
TX PLL
4
4
Receiver
PLLs
PLD
Global
Clocks
16
Transceiver Block 2
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
refclkb
/2
IQ2
Global Clks, I/O Bus, Gen Routing
TX PLL
4
Receiver
PLLs
(2)
4
Transceiver Block 3
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
refclkb
/2
IQ2
Global Clks, I/O Bus, Gen Routing
TX PLL
4
Receiver
PLLS
(2)
4
Notes to Figure 2–27:
(1) IQ lines are inter-transceiver block lines.
(2) If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed.
(3) There are four receiver PLLs in each transceiver block.
2–32
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006